1. Field of the Invention
The present invention relates generally to the field of digital design system verification and more specifically relates to advanced simulation techniques for digital system designs.
2. Related Art
In the electronic design automation (“EDA”) market today, the general design cycle for digital systems involves creating a design for the system, validating the design, and then manufacturing the system. The validation process is the focus of the present invention.
Currently, system designs are validated using one of two methodologies. The first method involves creating a physical hardware replica of the design on a test board. This method is referred to as emulation. In today's world of system-on-a-chip (“SOC”) designs, the emulation method is becoming increasingly untenable. Typically, the physical replication of a chip design on a test board uses discrete physical components to mimic components that the design engineers have integrated into the chip design. Therefore, an interface that does not exist in the design must be placed between the discrete components of the physical test board.
Because such an interface does not exist in the actual design, test boards are increasingly divergent from the designs they intend to replicate. Another drawback of using test boards is the lead time required to build a physical test board and the lead time required to create the necessary interfaces between the components of the system. This additional delay, which typically can be as much several months per test board, so significantly increases the time for each iterative refinement step in the design cycle that emulation is nearly too burdensome to be useful in today's competitive reduced time-to-market environment.
Additionally, interfaces to the memory components used on a test board are typically not the same as the memory interfaces used in the design. This is often due to the fact that test boards use standard memory chips rather than the actual memory incorporated into the design. The use of these standard memory chips and their attendant interfaces further deviates the physical test board model from the actual design. For at least these reasons, the use of physical test boards to emulate electronic system designs is not very desirable.
The second method for validating a system design involves running a system simulation model on a computer. In order to perform a simulation, the system design is typically modeled using a hardware description language (“HDL”) such as Verilog®. Alternatively, a system model can be created using the very high speed integrated circuit hardware description language (“VHDL”).
Simulations can be performed on an abstract HDL or VHDL (collectively “HDL”) based system model without the need for a physical hardware prototype. In this way, the behavior of a system design can be replicated in software such that a virtual simulation environment can accurately describe the characteristics of the newly designed system. Therefore, the typical problems associated with a physical test board can be overcome by executing an HDL system model in a virtual hardware simulation environment.
For example, it may only require a few days to create an HDL system model while creation of a physical test board typically may require several months. Also, it may only require a few hours to create an iterative second version HDL system model versus the several months required to create a similar second version test board.
Additionally, an HDL system model does not impose the use of non-existent interfaces between components because the model describes the components as they exist in the design. Furthermore, a HDL system model can accurately define the characteristics of the memory actually included in the design, rather than using standard memory modules. This eliminates the non conforming interfaces required by the use of standard memory chips on physical test boards.
However, although a system model has definite advantages over a physical test board, it has several drawbacks. With the growing complexity of systems comprising a mix of micro controllers, digital signal processors (“DSP”), random access memory (“RAM”), read only memory (“ROM”), dedicated logic, and various other interconnected components, the simulation of a system design has become a bottleneck in the total system design process. Complete system validation of an HDL system model is therefore impracticable for today's complex SOC devices.
Thus, a considerable drawback of an HDL system model is a significantly increased simulation time for complex SOC devices. For example, a physical test board will typically run about 10 times slower than the production version of the design being simulated. An HDL system model, on the other hand, will typically run about 1,000,000 times slower than the production version of the design being simulated. This significant difference in simulation speed considerably lengthens the amount of time needed for a system simulation environment to execute an HDL system model, thereby limiting the amount of system validation in today's reduced time-to-market environment.
Although in the past, moving to higher levels of abstraction and ignoring some level of detail in the system models has moderately increased the speed of simulations, the complexity of the designs being simulated has similarly increased. For example, in the late 1980's, gate level simulators typically offered a relatively low performance, measured in instructions per second (“IPS”). In the early 1990s, register transfer level (“RTL”) simulators considerably improved performance. More recent system models created in HDL have additionally improved performance. However, because today's more complex designs typically require thousands of lines of code and millions of clock cycles to validate any significant portion of the system design, an average simulation run may take hours or even days to complete.
Another drawback of the HDL system model is that virtual simulations are event driven. For example, to simulate a simple read instruction within a processor, an HDL system model creates several separate events. Cumulatively, all of these events require that the computer running the simulation environment execute an extremely large number of instructions, which in turn causes the HDL system model to run about 1,000,000 times slower than the production version of the design being simulated. Additionally, all of the events in a HDL system model create an extremely granular level of detail that is not required by a design engineer to examine the success of a system model during and after the simulation run.
In addition to simulating an HDL system model of hardware components within a system design, system design validations must also simulate the software components of a system design with integrated hardware and software components. For example, U.S. Pat. No. 5,768,567 describes an optimizing hardware and software co-simulator and U.S. Pat. No. 5,771,370 describes a method and apparatus for optimizing hardware and software co-simulation. However, each of these patents require the use of a discrete logic simulator simulation environment for the hardware components and a discrete instruction set simulation environment for the software components.
Therefore, what is needed is a method and apparatus that overcomes these significant problems found in the conventional systems as described above.